This invention relates to a semiconductor memory cell, array, architecture and device, and techniques for reading, controlling and/or operating such cell and device; and more particularly, in one aspect, to a semiconductor dynamic random access memory (“DRAM”) cell, array, architecture and/or device wherein the memory cell includes an electrically floating body in which an electrical charge is stored.
There is a continuing trend to employ and/or fabricate advanced integrated circuits using techniques, materials and devices that improve performance, reduce leakage current and enhance overall scaling. Silicon-on-Insulator (SOI) is a material in which such devices may be fabricated on or in (hereinafter collectively “on”). Such devices are known as SOI devices and include, for example, partially depleted (PD), fully depleted (FD) devices, multiple gate devices (for example, double or triple gate), and Fin-FET. SOI devices have demonstrated improved performance (for example, speed), reduced leakage current characteristics and considerable enhancement in scaling.
One type of dynamic random access memory cell is based on, among other things, a floating body effect of SOI transistors. (See, for example, U.S. patent application Ser. No. 10/450,238, Fazan et al., filed Jun. 10, 2003 and entitled “Semiconductor Device”, hereinafter “Semiconductor Memory Device Patent Application”). In this regard, the memory cell may consist of a PD or a FD SOI transistor (or transistor formed in bulk material/substrate) on having a channel, which is disposed adjacent to the body and separated therefrom by a gate dielectric. The body region of the transistor is electrically floating in view of the insulation or non-conductive region (for example, in bulk-type material/substrate) disposed beneath the body region. The state of memory cell is determined by the concentration of charge within the body of the transistor.
With reference to FIGS. 1A, 1B and 1C, in one embodiment, semiconductor DRAM array 10 includes a plurality of memory cells 12, each consisting of transistor 14 having gate 16, an electrically floating body region 18, source region 20 and drain region 22. The body region 18 is disposed between source region 20 and drain region 22. Moreover, body region 18 is disposed on or above region 24, which may be an insulation region (for example, in SOI material/substrate) or non-conductive region (for example, in bulk-type material/substrate). The insulation or non-conductive region may be disposed on substrate 26.
Data is written into or read from a selected memory cell by applying suitable control signals to a selected word line(s) 28, a selected source line(s) 30 and/or a selected bit line(s) 32. In response, charge carriers are accumulated in or emitted and/or ejected from electrically floating body region 18 wherein the data states are defined by the amount of carriers within electrically floating body region 18. Notably, the entire contents of the Semiconductor Memory Device Patent Application, including, for example, the features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are incorporated by reference herein.
As mentioned above, memory cell 12 of DRAM array 10 operates by accumulating in or emitting/ejecting majority carriers (electrons or holes) 34 from body region 18 of, for example, N-channel transistors. (See, FIGS. 2A and 2B). In this regard, accumulating majority carriers (in this example, “holes”) 34 in body region 18 of memory cells 12 via, for example, impact ionization near source region 20 and/or drain region 22, is representative of a logic high or “1” data state. (See, FIG. 2A). Emitting or ejecting majority carriers 30 from body region 18 via, for example, forward biasing the source/body junction and/or the drain/body junction, is representative of a logic low or “0” data state. (See, FIG. 2B).
Notably, for at least the purposes of this discussion, a logic high or State “1” corresponds to an increased concentration of majority carries in the body region relative to an unprogrammed device and/or a device that is programmed with a logic low or State “0”. In contrast, a logic low or State “0” corresponds to a reduced concentration of majority carries in the body region relative to an unprogrammed device and/or a device that is programmed with logic high or State “1”.
Several arrangements, layouts and techniques have been proposed to read and write the data stored in an electrically floating body type transistor. For example, a current sense amplifier may be employed to compare the cell current to a reference current, for example, the current of a reference cell. From that comparison, it is determined whether the memory cell contained a logic high data state (relatively more majority carriers contained within body region) or logic low data state (relatively less majority carriers contained within body region). The differences of the charge stored in the body of the transistor affect the threshold voltage of the transistor, which in turn affects the current conducted by the transistor when switched into its conductive state.
In particular, with reference to FIG. 3, sense amplifier 36 (for example, a cross-coupled sense amplifier) typically includes an input/output 38a connected to an associated bit line and an input 38b connected to a reference current generator 40. In operation, sense amplifier 36 compares the current conducted by transistor 14 of memory cell 12 with a reference current generated by reference current generator 40. The magnitude of the reference current generally lies between the magnitudes of the currents conducted in the logic high data state and logic low data state of memory cell 12. The sense amplifier 36 compares the reference current to the current produced by memory cell 12 (the current varies depending on whether memory cell 12 is either in a logic high data state or logic low data state). Based on that comparison, sense amplifier 36 generates or outputs an output signal (on output 42) having a positive or negative polarity, depending upon whether memory cell 12 stored a logic high or logic low binary data state. (See, for example, U.S. Pat. No. 6,567,330; and “Memory Design Using a One-Transistor Cell on SOI”, IEEE Journal of Solid-State Circuits, Vol. 37, No. 11, November 2002).
Conventional data sense circuitry/architectures and techniques of the prior art have a number of shortcomings. For example, the data sense circuitry/architecture and technique of the prior art requires a data sense circuit for each bit line. This results in a difficult pitch for implementing the sense amplifier design. (See, for example, U.S. Pat. Nos. 6,567,330 and 6,650,565). Such architectures often employ a pitch that is at least twice the pitch of the memory cell array. In addition, a large number of sense amplifiers are required if a large word line is employed to achieve dense memory arrays. This large number of sense amplifiers is generally not desirable since data from a subset of the number of cells is usually wanted/needed. This creates overhead in silicon area and power consumption.